View T-55343GD035JU-LW-ADN_5385631.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note application note T-55343GD035JU-LW-ADN 3.5inch tft transmissive optrex corporation pm division first edition yuchi okamoto nakazawa july 21, 08 0 modification issue check approval date revision www.datasheet.co.kr datasheet pdf - http://www..net/
2 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note index 1. application .page3 2. general specifications .page3 3. how to use 3.1 interface connection .page4 (1) lcd module side page4 (2)backlight side page4 3.2 brief of system circuit page5 3.3 driving the lcd module page6 (1) power on sequence page6 (2) power on register setting ..page7 (3) power off sequence page8 (4) power off register setting ..page8 (5) detail of register setting ..page9 driver output control (r01h) page9 lcddrivingwaveform control (r02h) ..page10 power control 1 (r03h) ..page11 input data and color filter control (r04h) .page13 function control (r05h) page14 contrast/brightness control (r0ah) page15 frame cycle control control (r0bh) ..page16 power control 2 (r0dh) .page17 power control 3 (r0eh) ... .....page19 gate scan position (r0fh) ...page20 horizontal porch (r16h) ....page21 vertical porch (r17h) .page22 power control 4 (r1eh) .page24 3.4 example of driving the lcd controller page26 3.5 example of driving the lcd controller page31 www.datasheet.co.kr datasheet pdf - http://www..net/
3 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note 1. application this application note applies to tft lcd module t55343gd035julwadn please see the detail spec at the specification she et of this lcd module. 2. general specifications 24bits digitalrgb 8bits/color serial interface image data 12ocolor angle of least color inversion viewing direction 79.0(w) 65.0(h) 3.2max* d mm *without fpc and component area outline dimension register interface ag coating surface treatment 29.5gmax normally white 16m color rgbstripe 0.073(w) 3[r,g,b] 0.219(h)mm 320(w) 3[r,g,b] 240(h) 70.08(w) 52.56(h) mm 3.5inches 8.9cm diagonal specification pixel size display mode weight color depth pixel arrangement display format active area screen size item www.datasheet.co.kr datasheet pdf - http://www..net/
4 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note 3. how to use 3.1 interface connection (1) lcd module side lcd module side is matched with 44conductor fpc / ffc to zif connector. one touch lock lock type 2.00mm height bottom contact contact location zero insertion force (zif) right angle cable connection 0.5 mm pitch pitch 40 pin numbers 046240040023846+ type number kyocera elco produced by (2) backlight side backlight side is matched with 3conductor fpc / ff c to zif connector. lock type height contact location cable connection pitch pin numbers type number produced by one touch lock 0.9mm bottom contact zero insertion force (zif) right angle 0.5 mm pitch 3 046298003000883 kyocera elco www.datasheet.co.kr datasheet pdf - http://www..net/
5 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note 3.2 brief of system circuit power supply zif connector exp. customers equipment circuit board power signal zif connector lcd module cpu or mpu lcd controller rom ram mcu or cpu led controller parallel i/f serial i/f www.datasheet.co.kr datasheet pdf - http://www..net/
6 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note 3.3 driving the lcd module (1) power on sequence we show the power on sequence for this lcd moduke. please see the specification sheet for t55264 for detail of timing value needed to operate the display. hsync vcc spi accessing reset spi dotclk vsync spi command sequence 1st 4th 11th black pattern normal pattern db0~ db23 >10s >10s display on vcc power on wait 10sec~ release reset input control signal (dotclk/hsync/vsync) execute spi command setting see the 2 power on register setting input black data lcd display on after 11 frames www.datasheet.co.kr datasheet pdf - http://www..net/
7 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note (2) power on register setting example for register setting. (recommended value) s no need to change after power on a need to change or adjust after power on s s s s s s s s s s a s s s s s s s s s s a s 0006h 3bh control10 0c00h 3ah control9 0703h 37h control8 0707h 36h control7 0001h 35h control6 0107h 34h control5 0307h 33h control4 0006h 32h control3 0607h 31h control2 0000h 30h control1 adjust the vcom. notp = 1 vcomh = 0.800 * vlcd63 101 1011 00dbh 1eh power control (4) 2212h 17h vertical porch 9f80h 16h horizontal porch 0000h 0fh gate scan starting position vcoma = 1.0875 * vlcd63 1 0001 01 3140h 0eh power control (3) vrc = 5.9 (vcix2) 0100 vdd = 2.2 (if pin "regvdd" is set to vddio) 0010 vlcd63 = vref * 4.408 (vref=1.25) 00111101 423dh 0dh power control (2) d400h 0bh frame cycle control 3f08h 0ah contrast/brightness control b0c4h 05h function control 0447h 04h data and color filter control step up-cycle fline*5 0110 vgh = (vcix2 * 3) vgl = -(vcix2 * 3) + vci 0000 step up-cycle fline*5 0110 opamp power small to medium 0100 6064h 03h power control (1) the grayscale level can be reversed. 0200h 02h lcd driver ac control line inversion 6300h 01h driver output control www.datasheet.co.kr datasheet pdf - http://www..net/
8 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note (3) power off sequence we show the example of power off sequence. hsync vcc spi accessing reset spi dotclk vsync spi command sequence 1st 6th white pattern normal pattern db0~ db23 execute spi command setting input white data lcd display off after 6 frames stop control signal (dotclk/hsync/vsync) vcc power off power control (1) 0003 h 0100 h index index index index v al ue v al ue v al ue v al ue setti ng item setti ng item setti ng item setti ng item (4) power off register setting. example of register setting. (recommended) www.datasheet.co.kr datasheet pdf - http://www..net/
9 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note driver output control (r01h) 0 ib00 0 ib02 0 ib03 0 ib01 0 ib04 0 ib05 0 ib06 0 ib07 cpe ib08 tb ib09 sm ib10 bgr ib11 pin v ib12 rev ib13 rl ib14 0 ib15 1 r/s w r/w cpe : cpe = 0 gate voltage source voltage vcom voltage are shut down cpe = 1 gate voltage source voltage vcom voltage are enabled. rev : grayscale level reverse setting. rev = 1 displays all character and graphics display sections with same data. rev = 0 displays all character and graphics display sections with reversal. pinv : pol ? ?B O pinv = 0 pol output is same phase with internal vcom signal. (generally set pol = 1) pinv = 1 pol output phase is reversed with vcom signal . bgr : select the [r][g][b] alignment. bgr = 0 [r][g][b] color is assigned from s0. generally set bgr = 0 bgr = 1 [b][g][r] color is assigned from s0. sm : set sm = 0 tb : rl : tb=0 rl=0 tb=1 rl=0 tb=0 rl=1 tb=1 rl=1 g1 g239 g0 g240 s0 s959 g1 g239 g0 g240 s0 s959 g1 g239 g0 g240 s0 s959 g1 g239 g0 g240 s0 s959 (5) detail of register setting www.datasheet.co.kr datasheet pdf - http://www..net/
10 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note lcddrivingwaveform control (r02h) 0 ib00 0 ib02 0 ib03 0 ib01 0 ib04 0 ib05 0 ib06 0 ib07 cpe ib08 b/c ib09 0 ib10 0 ib11 0 ib12 0 ib13 0 ib14 0 ib15 1 r/s w r/w b/c : select the lcd driving signal b/c = 0, frame inversion b/c = 1, line inversion ? please set b/c = 1. expand notenote of using line inversion compared to frame inversion, we can improve the ima ge quality lcd, when select the line inversion. when display the 1line black and gray border patter n, display show the stronger flicker. it is due to the line inversion is the driving meth od which is inverse each line. so, we highly recommend not to use this image for b ackground image. www.datasheet.co.kr datasheet pdf - http://www..net/
11 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note power control 1 (r03h) 0 ib00 ap1 ib02 ap2 ib03 ap0 ib01 dc0 ib04 dc1 ib05 dc2 ib06 dc3 ib07 bt0 ib08 bt1 ib09 bt2 ib10 btf ib11 dct 0 ib12 dct 1 ib13 dct 2 ib14 dct 3 ib15 1 r/s w r/w dct3-0 : set the stepup cycle of the stepup circuit for 8 color mode. *this lcd module cannot use 8 color mode, so ignore this register. please set dct3-0 = 0110. bt2-0btf : control the stepup factor of the stepup circuit. adjust the stepup factor according to the power supply voltage to be used. generally set btf,2-0=0000. vcix2j vcix2j x 3 x x x 1 (vcix2j x 2) + vci vcix2j x 2 1 1 1 0 (vcix2j x 2) + vci vcix2j x 2 + vci 1 0 1 0 (vcix2j x 2) vcix2j x 2 0 1 1 0 (vcix2j x 2) vcix2j x 2 + vci 0 0 1 0 (vcix2j x 2) + vci vcix2j x 2 + vci 1 1 0 0 (vcix2j x 3) vcix2j x 3 0 1 0 0 (vcix2j x 2) vcix2j x 3 1 0 0 0 (vcix2j x 2) + vci vgl output vgh output vcix2j x 3 0 bt0 0 bt1 0 bt2 0 btf www.datasheet.co.kr datasheet pdf - http://www..net/
12 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note dc30 : set the stepup cycle of the stepup circuit for 262kcolor mode. color mode is always fixed as 262 color mode in th is module. when the cycle is accelerated, the driving ability of the stepup circuit are increase, but their curr ent consumption increase, too. adjust the cycle taking into account the display quality and power consumption. generally set dc30 = 0110. ap2-0 : adjust the amount of current from the stablecurren t source in the internal operational amplifier circuit. when the amount of current becomes large, the driving ability of the operationalamplifier circuits increase. adjust the current taking into a ccount the power consumption. during times when there is no display, such as when the system is in a sleep mode , set ap20 = 000 to halt the operational amplifie r circuit and the stepup circuits to reduce current consumption. fline x 2 1 0 0 1 fline x 1 0 1 0 1 fline x 0.5 1 1 0 1 fline x 0.25 0 0 1 1 reserved 1 0 1 1 reserved 0 1 1 1 reserved 1 1 1 1 fline x 3 0 0 0 1 fline x 4 1 1 1 0 fline x 5 0 1 1 0 fline x 6 1 0 1 0 fline x 7 0 0 1 0 fline x 8 1 1 0 0 fline x 10 0 1 0 0 fline x 12 1 0 0 0 fline x 14 stepup cycle 0 dc0 0 dc1 0 dc2 0 dc3 large to maximum 0 1 1 small to medium 0 1 0 medium 1 1 0 medium to large 0 0 1 large 1 0 1 maximum small least opamp power 1 1 0 ap0 1 0 0 ap1 1 0 0 ap2 www.datasheet.co.kr datasheet pdf - http://www..net/
13 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note input data and color filter control (r04h) sw d0 ib00 sw d2 ib02 sel 0 ib03 sw d1 ib01 sel 1 ib04 sel 2 ib05 oea 0 ib06 oea 1 ib07 blt 0 ib08 blt 1 ib09 pal m ib10 0 ib11 0 ib12 0 ib13 0 ib14 0 ib15 1 r/s w r/w swd20 : select the tft alignment, delta or stripe. this lcd module is stripe alignment, so please set swd20 = 111 sel20 : define the input interface mode. this lcd module supports parallelrgb data format, so please set sel20 = 000. blt10 : set the initial power on black image inser tion time. 00 : 10 fields ? generally set blt10 = 00 01 : 20 fields 10 : 40 fields 11 : 80 fields palm : set the input data line number in pal mode 0 : 280 lines 1 : 288 lines oea10 : odd/even field advanced function. generally set oea10 = 00 no use 1 1 display start @ vbp delay for odd field and @ vbp+1 for even field. 0 1 display start @ vbp delay for odd field and @ vbp for even field. 1 0 display start @ vbp delay for odd field and @ vbp-1 for even field. 0 0 oea0 oea1 www.datasheet.co.kr datasheet pdf - http://www..net/
14 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note function control (r05h) fb0 ib00 fb2 ib02 0 ib03 fb1 ib01 pw m ib04 0 ib05 dit ib06 deo ib07 hsp ib08 vsp ib09 ckp ib10 dep ib11 lpf ib12 gdi s ib13 xdk ib14 ghn ib15 1 r/s w r/w fb20 : set pwm feedback level adjustment. *in this lcd module, no function for pwm. so, pleas e set fb20=000. pwm : set pwm feedback level adjustment. pwm=0 : pwm off pwm=1 : pwm on *in this lcd module, no function for pwm. so, pleas e set pwm=0 O ? dit : set the dithering function. dit=0 : dithering of f dit=1 : dithering on use 24bits : dit = 1 use 18bits : dit = 0 deo : set de mode. deo = 0 : vsync/hsync are also needed in de mode. und er this condition, vertical back porch is defined by vbp [6:0] and the horizontal fi rst valid data is defined by de signal. deo=1, only den signal is needed in de mode. hsp : set the polarity of hsync.hsp=0, negative polar ity hsync. hsp=1, positive polarity hsync. vsp : set the polarity of hsync.vsp=0, negative pola rity vsync. vsp=1, positive polarity vsync. ckp : set the direction of data latch of clk. ckp = 0, data is latched in clk falling edge. ckp = 1, data is latched in clk rising edge. dep : set the polarity of den. dep=0, den negative p olarity active. dep=1, den negative polarity active. lpf : set the low pass filter in yuv mode. *this lcd doesnt support the yuv interface, so ple ase ignore this register. gdis : set the discharge of vgl. gdis=0, vgl has no discharge path to vss in sleep m ode. gdis=1, vgl will discharge to vss in sleep mode. when cpe=0, gdis is fixed to 0, and you cant change it by spi. xdk : set the pumping way of vcix2 xdk=0, vcix2 is 2 stage pumping from vci. (vcix2 = 3 x vci) xdk=1, vcix2 is 2 phase pumping from vci. (vcix2 = 2 x vci) ghn : set the output of vgh. ghn=0, all gate outputs are forced to vgh. ghn=1, gate driver is normal operation. www.datasheet.co.kr datasheet pdf - http://www..net/
15 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note contrast/brightness control (r0ah) con 0 ib00 con 2 ib02 con 3 ib03 con 1 ib01 con 4 ib04 0 ib05 0 ib06 0 ib07 br0 ib08 br1 ib09 br2 ib10 br3 ib11 br4 ib12 br5 ib13 br6 ib14 0 ib15 1 r/s w r/w con40 : display contrast level adjustment. (0.125/s tep) adjust range from 00h (level = 0) to 1fh (level = 3.875). generally s et con40=1000. br60 : display brightness level adjustment. (2/step ) adjust range from 00h (level = 128) to 7fh (level = +126). generally set br60 = 3fh www.datasheet.co.kr datasheet pdf - http://www..net/
16 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note frame cycle control control (r0bh) 0 ib00 0 ib02 0 ib03 0 ib01 0 ib04 0 ib05 0 ib06 0 ib07 eq0 ib08 eq1 ib09 eq2 ib10 0 ib11 sdt 0 ib12 sdt 1 ib13 no0 ib14 no1 ib15 1 r/s w r/w no10 : set amount of nonoverlap of the gate output . set no10 = 01 6us 4.5us 3us 1.5us non-overlap 1 0 1 0 no0 1 1 0 0 no1 std10 : set delay amount from the gate output signa l falling edge to the source outputs. set std10 = 00 7us 5us 3us 1us delay 1 0 1 0 std0 1 1 0 0 std1 eq20 : sets the equalizing period. set eq20 = 000 9us 1 1 1 8us 0 1 1 7us 1 0 1 6us 0 0 1 5us 1 1 0 4us 0 1 0 3us 1 0 0 no eq eq period 0 eq0 0 eq1 0 eq2 www.datasheet.co.kr datasheet pdf - http://www..net/
17 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note power control 2 (r0dh) vrh 0 ib00 vrh 2 ib02 vrh 3 ib03 vrh 1 ib01 vrh 4 ib04 vrh 5 ib05 0 ib06 0 ib07 vds 0 ib08 vds 1 ib09 0 ib10 0 ib11 vrc 0 ib12 vrc 1 ib13 vrc 2 ib14 0 ib15 1 r/s w r/w vrc20 : set the vcix2 charge pump voltage clamp vrc [2:0]=000, 5.1v vrc [2:0]=001, 5.3v vrc [2:0]=010, 5.5v vrc [2:0]=011, 5.7v vrc [2:0]=100, 5.9v vrc [2:0]=101, reserved vrc [2:0]=110, reserved vrc [2:0]=111, reserved vds1:0 : set the vdd regulator voltage if pin regv dd is set to vddio. vds [1:0]=00, 1.8v vds [1:0]=01, 2.0v vds [1:0]=10, 2.2v vds [1:0]=11, 2.5v vrh50 : set amplitude magnification of vlcd63. vref = 1.25v www.datasheet.co.kr datasheet pdf - http://www..net/
18 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note vref x 3.448 1 1 1 1 1 0 vref x 3.416 0 1 1 1 1 0 vref x 3.384 1 0 1 1 1 0 vref x 2.936 1 1 1 1 0 0 vref x 2.904 0 1 1 1 0 0 vref x 2.872 1 0 1 1 0 0 vref x 2.968 0 0 0 0 1 0 vref x 3.000 1 0 0 0 1 0 vref x 3.032 0 1 0 0 1 0 vref x 3.064 1 1 0 0 1 0 vref x 3.096 0 0 1 0 1 0 vref x 3.128 1 0 1 0 1 0 vref x 3.160 0 1 1 0 1 0 vref x 3.192 1 1 1 0 1 0 vref x 3.224 0 0 0 1 1 0 vref x 3.256 1 0 0 1 1 0 vref x 3.288 0 1 0 1 1 0 vref x 3.320 1 1 0 1 1 0 vref x 3.352 0 0 1 1 1 0 vref x 2.840 0 0 1 1 0 0 vref x 2.808 1 1 0 1 0 0 vref x 2.776 0 1 0 1 0 0 vref x 2.744 1 0 0 1 0 0 vref x 2.712 0 0 0 1 0 0 vref x 2.680 1 1 1 0 0 0 vref x 2.648 0 1 1 0 0 0 vref x 2.616 1 0 1 0 0 0 vref x 2.584 0 0 1 0 0 0 vref x 2.552 1 1 0 0 0 0 vref x 2.520 0 1 0 0 0 0 vref x 2.488 1 0 0 0 0 0 vref x 2.456 vlcd63 voltage 0 vrh 0 0 vrh 1 0 vrh 2 0 vrh 3 0 vrh 4 0 vrh 5 vref x 4.472 1 1 1 1 1 vref x 4.440 0 1 1 1 1 vref x 4.408 1 0 1 1 1 vref x 3.960 1 1 1 1 0 1 vref x 3.928 0 1 1 1 0 1 vref x 3.896 1 0 1 1 0 1 vref x 3.992 0 0 0 0 1 1 vref x 4.024 1 0 0 0 1 1 vref x 4.056 0 1 0 0 1 1 vref x 4.088 1 1 0 0 1 1 vref x 4.120 0 0 1 0 1 1 vref x 4.152 1 0 1 0 1 1 vref x 4.184 0 1 1 0 1 1 vref x 4.216 1 1 1 0 1 1 vref x 4.248 0 0 0 1 1 1 vref x 4.280 1 0 0 1 1 1 vref x 4.312 0 1 0 1 1 1 vref x 4.344 1 1 0 1 1 1 vref x 4.376 0 0 1 1 1 1 vref x 3.864 0 0 1 1 0 1 vref x 3.832 1 1 0 1 0 1 vref x 3.800 0 1 0 1 0 1 vref x 3.768 1 0 0 1 0 1 vref x 3.736 0 0 0 1 0 1 vref x 3.704 1 1 1 0 0 1 vref x 3.672 0 1 1 0 0 1 vref x 3.640 1 0 1 0 0 1 vref x 3.608 0 0 1 0 0 1 vref x 3.576 1 1 0 0 0 1 vref x 3.544 0 1 0 0 0 1 vref x 3.512 1 0 0 0 0 1 vref x 3.480 vlcd63 voltage 0 vrh 0 0 vrh 1 0 vrh 2 0 vrh 3 0 vrh 4 1 vrh 5 www.datasheet.co.kr datasheet pdf - http://www..net/
19 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note power control 3 (r0eh) 0 ib00 0 ib02 0 ib03 0 ib01 0 ib04 0 ib05 vdv 0 ib06 vdv 1 ib07 vdv 2 ib08 vdv 3 ib09 vdv 4 ib10 vdv 5 ib11 vdv 6 ib12 1 ib13 0 ib14 0 ib15 1 r/s w r/w vdv60 : set the alternating amplitudes of vcom at the vcom alternating drive. reserved * * * * 1 0 1 reserved * * 1 1 1 0 1 vlcd63 x 1.2525 1 1 0 1 1 0 1 vlcd63 x 1.2450 0 1 0 1 1 0 1 step = 0.0075 ???? vlcd63 x 1.0575 1 0 0 0 0 0 1 vlcd63 x 1.0500 0 0 0 0 0 0 1 reference from external voltage (vcomr) * * 1 1 1 1 0 vlcd63 x 1.0425 1 1 0 1 1 1 0 vlcd63 x 1.0350 0 1 0 1 1 1 0 step = 0.0075 ???? vlcd63 x 0.6300 0 0 1 0 0 0 0 vlcd63 x 0.6225 1 1 0 0 0 0 0 vlcd63 x 0.6150 0 1 0 0 0 0 0 vlcd63 x 0.6075 1 0 0 0 0 0 0 vlcd63 x 0.6000 vcom amplitude 0 vdv0 0 vdv1 0 vdv2 0 vdv3 0 vdv4 0 vdv5 0 vdv6 www.datasheet.co.kr datasheet pdf - http://www..net/
20 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note gate scan position (r0fh) scn 0 ib00 scn 2 ib02 scn 3 ib03 scn 1 ib01 scn 4 ib04 scn 5 ib05 scn 6 ib06 scn 7 ib07 0 ib08 0 ib09 0 ib10 0 ib11 0 ib12 0 ib13 0 ib14 0 ib15 1 r/s w r/w scn80 : set the scanning starting position of the gate driver. g0 g239 1 st line of data optrex corporation scn70 = 00000000 g0 g239 1 st line of data optrex corporation scn70 = 00011110 g30 www.datasheet.co.kr datasheet pdf - http://www..net/
21 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note horizontal porch (r16h) 0 ib00 0 ib02 0 ib03 0 ib01 0 ib04 0 ib05 0 ib06 xli m0 ib07 xli m1 ib08 xli m2 ib09 xli m3 ib10 xli m4 ib11 xli m5 ib12 xli m6 ib13 xli m7 ib14 xli m8 ib15 1 r/s w r/w xlim80 : set the scanning starting position of the gate driver. 320 1 1 1 1 1 1 0 0 1 reserved * * * * * 1 0 0 1 * 0 0 0 0 xlim6 1 0 0 0 0 xlim7 reserved * * * * * * 1 319 0 1 1 1 1 1 1 step = 1 ???? ???? ???? 3 0 1 0 0 0 0 0 2 1 0 0 0 0 0 0 1 no. of pixel per line 0 xlim0 0 xlim1 0 xlim2 0 xlim3 0 xlim4 0 xlim5 0 xlim8 www.datasheet.co.kr datasheet pdf - http://www..net/
22 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note vertical porch (r17h) vbp 0 ib00 vbp 2 ib02 vbp 3 ib03 vbp 1 ib01 vbp 4 ib04 vbp 5 ib05 vbp 6 ib06 hbp 0 ib07 hbp 1 ib08 hbp 2 ib09 hbp 3 ib10 hbp 4 ib11 hbp 5 ib12 hbp 6 ib13 sth 0 ib14 sth 1 ib15 1 r/s w r/w hbp60 : set the number of valid pixel per line. 0 1 0 0 0 0 10 1 127 1 1 1 1 1 1 1 126 0 1 1 1 1 1 1 step C 1 ???? 9 1 0 0 0 0 0 1 cant set 0 0 0 1 0 0 0 cant set 1 1 1 0 0 0 0 cant set 0 1 1 0 0 0 0 cant set 1 0 1 0 0 0 0 cant set 0 0 1 0 0 0 0 cant set 1 1 0 0 0 0 0 cant set 0 1 0 0 0 0 0 cant set 1 0 0 0 0 0 0 cant set no. of clock cycle 0 hbp0 0 hbp1 0 hbp2 0 hbp3 0 hbp4 0 hbp5 0 hbp6 set by xlim 80 set by hbp cycle time of hsync set by vbp cycle time of vsync display area www.datasheet.co.kr datasheet pdf - http://www..net/
23 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note sth10 : adjust the first valid data by dot clock. * this setting is not valid in parallel rgb input i nterface. please ignore this setting. sth = 00: + 0 dot clock sth = 01: + 1 dot clock sth = 10: + 2 dot clock sth = 11: + 3 dot clock vbp60 : set the delay period from falling edge of vsync to first valid line. 127 1 1 1 1 1 1 1 126 0 1 1 1 1 1 1 step C 1 ???? 4 0 0 1 0 0 0 0 3 1 1 0 0 0 0 0 2 0 1 0 0 0 0 0 cant set 1 0 0 0 0 0 0 cant set no. of clock cycle 0 vbp0 0 vbp1 0 vbp2 0 vbp3 0 vbp4 0 vbp5 0 vbp6 www.datasheet.co.kr datasheet pdf - http://www..net/
24 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note power control 4 (r1eh) vcm 0 ib00 vcm 2 ib02 vcm 3 ib03 vcm 1 ib01 vcm 4 ib04 vcm 5 ib05 vcm 6 ib06 not p ib07 0 ib08 0 ib09 0 ib10 0 ib11 0 ib12 0 ib13 0 ib14 0 ib15 1 r/s w r/w notp : notp = 0 vcomh voltage equals to programmed otp value. notp = 1 setting of vcm60 becomes valid and voltage of vcomh can be adjusted. vcm6-0 : set the vcomh voltage if notp = 1. vlcd63 x 0.995 1 1 1 1 1 1 1 vlcd63 x 0.990 0 1 1 1 1 1 1 step = 0.005 ???? vlcd63 x 0.380 0 0 1 0 0 0 0 vlcd63 x 0.375 1 1 0 0 0 0 0 vlcd63 x 0.370 0 1 0 0 0 0 0 vlcd63 x 0.365 1 0 0 0 0 0 0 vlcd63 x 0.360 vcomh 0 vcm0 0 vcm1 0 vcm2 0 vcm3 0 vcm4 0 vcm5 0 vcm6 note about the adjustment of vcomh vcom is not adjusted to optimum value in this model . therefore, it is necessary to adjust the vcomh value. to adjust the vcomh, display the gray and black border line. and please set the valu e which minimize the flicker. www.datasheet.co.kr datasheet pdf - http://www..net/
25 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note gamma control 1 (r30h to r37) prn 00 prn 01 prn 02 0 0 0 0 0 prn 10 prn 11 prn 12 0 0 0 0 0 1 w pkn 40 pkn 41 pkn 42 0 0 0 0 0 pkn 50 pkn 51 pkn 52 0 0 0 0 0 1 w pkn 20 pkn 21 pkn 22 0 0 0 0 0 pkn 30 pkn 31 pkn 32 0 0 0 0 0 1 w pkn 00 pkn 01 pkn 02 0 0 0 0 0 pkn 10 pkn 11 pkn 12 0 0 0 0 0 1 w frp 00 frp 01 frp 02 0 0 0 0 0 frp 10 frp 11 frp 12 0 0 0 0 0 1 w pkp 40 pkp 41 pkp 42 0 0 0 0 0 pkp 50 pkp 51 pkp 52 0 0 0 0 0 1 w pkp 20 pkp 21 pkp 22 0 0 0 0 0 pkp 30 pkp 31 pkp 32 0 0 0 0 0 1 w pkp 00 pkp 01 pkp 02 0 0 0 0 0 pkp 10 pkp 11 pkp 12 0 0 0 0 0 1 w ib00 ib02 ib03 ib01 ib04 ib05 ib06 ib07 ib08 ib09 ib10 ib11 ib12 ib13 ib14 ib15 r/s r/w pkp52C00 : gamma micro adjustment registers for the positive polarity output. prp1200 : gradient adjustment registers for the pos itive polarity output. pkn5200 : gamma micro adjustment registers for the negative polarity output. prn1200 : gradient adjustment registers for the neg ative polarity output. vrn 00 vrn 01 vrn 02 vrn 03 0 0 0 0 vrn 10 vrn 11 vrn 12 vrn 13 vrn 14 0 0 0 1 w vrp 00 vrp 01 vrp 02 vrp 03 0 0 0 0 vrp 10 vrp 11 vrp 12 vrp 13 vrp 14 0 0 0 1 w ib00 ib02 ib03 ib01 ib04 ib05 ib06 ib07 ib08 ib09 ib10 ib11 ib12 ib13 ib14 ib15 r/s r/w vrp14C00 : adjustment registers for amplification ad justment of the positive polarity output. vrn14C00 : adjustment registers for the amplificatio n adjustment of the negative polarity output. www.datasheet.co.kr datasheet pdf - http://www..net/
26 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note 3.4 example of driving the lcd controller you can use lcd controller for digital rgb interfac e. part name s1d13743 (seiko epson) this manufacturers are presented for information on ly. optrex has not tested the performance and reliabili ty of their products and makes no warranty to their fitness for use. 2 connection show the wiring between this lcd module and the lcd controller. case1 18bits db11(vd9) 44 20 db12(vd10) 48 19 db13(vd11) 51 18 db14(vd12) 56 17 db15(vd13) 61 16 gnd 2 ? 15 db16(vd20) 55 14 db17(vd21) 60 13 db18 vd16 20 12 db19 vd17 40 11 db20 vd18 45 10 db21(vd19) 50 9 db22 vd20 55 8 db23(vd21) 60 7 enable (de) 3 6 hsync (hs) 4 5 vsync (vs) 5 4 dotclock (pclk) 8 3 tb ` 2 rl symbol name (s1d side) ` pin no. s1d15743 1 this module pin no. vcc(piovdd) 1 ? 40 vcc(piovdd) 1 ? 39 gnd 2 ? 38 sdo ` 37 reset ` 36 cs ` 35 scl ` 34 sdi ` 33 db0(db4) 57 32 db1(db5) 62 31 db2(db0) 39 30 db3(db1) 43 29 db4(db2) 49 28 db5(db3) 54 27 db6(db4) 57 26 db7(db5) 62 25 gnd 2 ? 24 db8(vd12) 56 23 db9(vd13) 61 22 db10(vd8) symbol name (s1d side) 38 pin no. s1d15743 21 this module pin no. www.datasheet.co.kr datasheet pdf - http://www..net/
27 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note case2 24bits symbol name (s1d side) pin no. s1d15743 this module pin no. db11(vd11) 51 20 db12(vd12) 56 19 db13(vd13) 61 18 db14(vd14) 15 17 db15(vd15) 14 16 gnd 2? 15 db16(vd16) 20 14 db17(vd17) 40 13 db18vd18 45 12 db19vd19 50 11 db20vd20 55 10 db21(vd21) 60 9 db22vd22 13 8 db23(vd23) 12 7 enable (de) 3 6 hsync (hs) 4 5 vsync (vs) 5 4 dotclock (pclk) 8 3 tb ` 2 rl ` 1 symbol name (s1d side) pin no. s1d15743 this module pin no. vcc(piovdd) 1? 40 vcc(piovdd) 1? 39 gnd 2? 38 sdo ` 37 reset ` 36 cs ` 35 scl ` 34 sdi ` 33 db0(db0) 39 32 db1(db1) 43 31 db2(db2) 49 30 db3(db3) 54 29 db4(db4) 57 28 db5(db5) 62 27 db6(db6) 63 26 db7(db7) 21 25 gnd 2? 24 db8(vd8) 38 23 db9(vd9) 44 22 db10(vd10) 48 21 www.datasheet.co.kr datasheet pdf - http://www..net/
28 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note 5.4 c code the following example scripts //------------------------------------------------ // t55343(3.5inch:320x240dots) //------------------------------------------------ //poweron_sequence power on setting //poweroff_sequence power off setting //display_output image display setting //please use the header file for each development e nvironment. //************************************************* ******** void transfer_s1d13743(short reg ,short data) { //-------------------------------------- // index register write(intel80 16bit) clear_bit( io_dc ); //dc low pararel_16bitout( reg ); //-------------------------------------- // instruction write(intel80 16bit) set_bit( io_dc ); //dc high pararel_16bitout( data ); } //************************************************* ******** void transfer_hx8238(short reg ,short data) { //-------------------------------------- // index register write(spi 24bit) clear_bit( io_csb ); //csb low spi_8bitout( 0x70 ); //deviceid,rs=0,rw=0 spi_8bitout( hibyte(reg) ); spi_8bitout( lobyte(reg) ); set_bit( io_csb ); //csb high //-------------------------------------- // instruction write(spi 24bit) clear_bit( io_csb ); //csb low spi_8bitout( 0x72 ); //deviceid,rs=1,rw=0 spi_8bitout( hibyte(data) ); spi_8bitout( lobyte(data) ); set_bit( io_csb ); //csb high } www.datasheet.co.kr datasheet pdf - http://www..net/
29 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note //************************************************* ******** // the reference setting of power on // 320x240dots 18-bit tft panel // corevdd = pllvdd =1.50v input // iovdd = piovdd =3.30v input // clki = 4.096mhz // sysclk = 49.152mhz //************************************************* ******** void poweron_sequence(void) { clear_bit( io_res ); //reset low delay_ms(1); //1ms wait set_bit( io_res ); //reset high delay_ms(10); //10ms wait //================================================= ==== // s1d13743 intialize //================================================= ==== transfer_s1d13743(0x56 ,0x02);//reg[56h] enter slee p mode //-------- clk configuraion -------- transfer_s1d13743(0x04 ,0x03);//reg[04h] pll m-divi der //pllin=clki/4=1.024mhz transfer_s1d13743(0x06 ,0xf8); //reg[06h] pll settin g 0 transfer_s1d13743(0x08 ,0x80);//reg[08h] pll settin g 1 transfer_s1d13743(0x0a ,0x28); //reg[0ah] pll setting 2 transfer_s1d13743(0x0c ,0x00);//reg[0ch] pll setting 3 transfer_s1d13743(0x0e ,0x2f); //reg[0eh] pll setting 4 //ll=48 pllclk=49.152mhz transfer_s1d13743(0x12 ,0x31);//reg[12h] clock sour ce select //pclk=7.022mhz sysclk=49.152mhz //-------- panel configuraion -------- //flm = 7.022mhz/(320+88)/(240+22) = 65.69hz //1clk(r6,g6,b6)=18bit transfer_s1d13743(0x14 ,0x00);//reg[14h] panel type //0b:18bit /1b:24bit transfer_s1d13743(0x16 ,0x28);//reg[16h] horizontal display width //hdp = 320 transfer_s1d13743(0x18 ,0x58);//reg[18h] horizontal non- display period //hndp = 88 transfer_s1d13743(0x1a ,0xf0); //reg[1ah] vertical d isplay height 0 transfer_s1d13743(0x1c ,0x00);//reg[1ch] vertical d isplay height 1 //vdp = 240 transfer_s1d13743(0x1e ,0x16);//reg[1eh] vertical n on-display period //vndp = 22 transfer_s1d13743(0x20 ,0x10);//reg[20h] hs pulse w idth //hsw = 16 pixels transfer_s1d13743(0x22 ,0x20);//reg[22h] hs pulse s tart position //hps = 32 pixels transfer_s1d13743(0x24 ,0x02);//reg[24h] vs pulse w idth //vsw = 2 lines transfer_s1d13743(0x26 ,0x04);//reg[26h] vs pulse s tart position //vps = 4 lines transfer_s1d13743(0x28 ,0x80);//reg[28h] pclk polari ty //80h: transfer_s1d13743(0x2a ,0x02); //reg[2ah] input mode //rgb 6:6:6 //-------- gpio configuraion -------- //gpio0=rl , gpio1=tb transfer_s1d13743(0x5a ,0x03); //reg[5ah] gpio confi guration //b1-0 output transfer_s1d13743(0x5c ,0x03);//reg[5ch] gpio port //tb=1 , rl=1 transfer_s1d13743(0x56 ,0x00);//reg[56h] disable sl eep mode delay_ms(10); //10ms wait www.datasheet.co.kr datasheet pdf - http://www..net/
30 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note //================================================= ==== // hx8238 intialize //================================================= ==== transfer_hx8238(0x1e ,0x00d0); //reg[1eh] power cont rol 4 //notp=1,vcm=1010000b transfer_hx8238(0x05 ,0xbcc4); //reg[05h] function c ontrol //dep=1 } //************************************************* ******** // the reference setting of power off //************************************************* ******** void poweroff_sequence(void) { transfer_s1d13743(0x56 ,0x02);//reg[56h] enter slee p mode delay_ms(100); //100ms wait clear_bit( io_res ); //reset low} //************************************************* ******** // write the image data to the memory data port //************************************************* ******** void display_output(short xdot ,short ydot) { short x,y; //-------- window aria set ---------- transfer_s1d13743(0x38 ,0x00); //reg[38h] window x s tart position0 transfer_s1d13743(0x3a ,0x00); //reg[3ah] window x s tart position1 transfer_s1d13743(0x3c ,0x00); //reg[3ch] window y s tart position0 transfer_s1d13743(0x3e ,0x00); //reg[3eh] window y s tart position1 transfer_s1d13743(0x40 ,lobyte(xdot-1)); //reg[40h] w indow x end position0 transfer_s1d13743(0x42 ,hibyte(xdot-1)); //reg[42h] window x end position1 transfer_s1d13743(0x44 ,lobyte(ydot-1)); //reg[44h] w indow y end position0 transfer_s1d13743(0x46 ,hibyte(ydot-1)); //reg[46h] window y end position1 clear_bit( io_dc ); //dc low pararel_16bitout( 0x48 ); //reg[48h] set_bit( io_dc ); //dc high //-------- bit map data out ---------- // 1dot=18bpp=rrrrrrxx ggggggxx bbbbbbxx // 1dot=24bpp =rrrrrrrr gggggggg bbbbbbbb for(y=0 ; y 31 confidential confidential 0 july 21, 2008 rev date t55343gd035julwadn application note 3.5 example of driving the led controller you can use led controller for backlight driving. part name lt3591 linear technology this manufacturers are presented for information on ly. optrex has not tested the performance and reliabili ty of their products and makes no warranty to their fitness for use. ctrl cap led gnd sw vin 3.3v shutdown and dimming control 22uh 1uf 2.2uf 10ohm a k led backlight the led current can be programmed by as follow. i led = 200mv / r sense i led =20ma www.datasheet.co.kr datasheet pdf - http://www..net/

▲Up To Search▲

Price & Availability of T-55343GD035JU-LW-ADN

	To Download T-55343GD035JU-LW-ADN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .